1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with buried gates.
2. Description of the Related Art
As the open areas (e.g., exposed surfaces) of a bit line contact and a storage node contact decrease, it becomes difficult to form a landing plug in a process of forming a buried gate in a cell region when a Dynamic Random Access Memory (DRAM) device is fabricated.
To facilitate the formation of a landing plug, a method of forming a landing plug before a gate is formed in a peripheral region is suggested.
FIG. 1 is a cross-sectional view illustrating a structure of a conventional semiconductor device.
Referring to FIG. 1, a device isolation layer 12 is formed over a substrate 11, and trenches 13 are formed by simultaneously etching the substrate 11 and the device isolation layer 12. A gate insulation layer 14 is formed on the surface of the trenches 13, and buried gates 15 each of which fills a portion of each trench 13 are formed. Subsequently, landing plugs 16 isolated by the trenches 13 are formed over the substrate 11, and storage node contact plugs 17 are formed over the landing plugs 16. A sealing layer 18 and a gap-fill layer 19 are disposed over the buried gates 15 to fill the trenches 13. The storage node contact plugs 17 penetrate through an inter-layer dielectric layer 20 to be coupled with the landing plugs 16.
In FIG. 1, the landing plugs 16 and the storage node contact plugs 17 are formed of polysilicon, and the polysilicon is doped with a dopant, such as phosphorus (P), to increase contact resistance.
However, when the concentration of the dopant of the storage node contact plugs 17 is increased to increase a cell contact resistance, the amount of dopant diffused into the substrate 11 is increased. In this case, the refresh performance of the semiconductor device may be deteriorated due to an increase of an electric field in a cell junction.
Conversely, when the concentration of the dopant of the storage node contact plugs 17 is decreased, the semiconductor device may have high refresh performance because the amount of dopant diffused into the substrate 11 is decreased, but the cell contact resistance is decreased.
Thus, the cell contact resistance and refresh performance are in a trade-off relationship.